Thomas Ernst is Chief Scientist and VP Research at CEA-Leti, responsible for long-term strategy and academic partnerships. He holds an engineering degree, a Ph.D., and a doctoral supervision accreditation from Grenoble Institute of Technology. He is a Senior Member of IEEE and a member of Academia Europaea. Dr. Ernst began his career with advanced SOI CMOS modeling at STMicroelectronics and CNRS. At CEA-Leti, he led major projects with industry partners like SOITEC, IBM, and NXP and collaborated with the start-up APIX on gas sensing technology under an ERC grant. In 2006, he and his team developed the first 3D stacked Gate-All-Around nanosheet transistors, contributing to sub-5 nm technology. He has also worked on reducing the environmental impact of electronics and has authored over 180 papers, holds 20 patents, and participated in key conference committees, including as ESSERC general chair.